Your task for this assignment is to implement a 16 bit CPU. To make the assignment feasible within the time frame available for this module, the type of CPU will be fairly simple. In particular, the “program sequencing/control flow instruction” datapath can be modeled after the one on the left of Figure 1, while the “arithmetic/logic instruction” datapath can follow a structure like the one on the right in the same figure. Please notice that when RAE and/or RBE is low, the corresponding output(s) will simply match the input “I” to the register file. The opcodes for the instructions that the CPU is required to implement are given in Table 1. You are also required to implement a decode unit in the control unit to interpret the ‘Effects’ and control signals from the output of each instruction.
Figure 1: The figure shows the “program sequencing/control flow instruction” datapath and the “arithmetic/logic instruction” datapath (right).
To test your CPU, you will design the main entity that instantiates the CPU and connects it to the Basys3 peripherals. The sixteen switches of the Basys3 board will represent the input to the CPU while its output will be shown as a hexadecimal number in the four digits of the 7-segment display. The central button will be used as a reset signal to the CPU.
To test the CPU you will be asked to code two programs in the assembly and machine languages of the CPU, implementing the following tasks
Given a nonzero number N as input, output the sum of the natural numbers less than N;
Given a number N as input, output “N div 11” (i.e. the integer quotient of the division between N and 11, “TRUNC(N/11)”);
These design specifications should be interpreted as guidelines and should not constrain you from improving the CPU by doing modifications that you think would result in a better “product”. The test programs above, though, should be implemented using only the instructions in Table 1. You are welcome to implement more elaborated programs to test the capabilities and the limitations of the CPU.
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